Verilog HDL - A Guide to Digital Design and Synthesis

Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Edition (ISBN 013-044911-3) is a popular book written by Samir Palnitkar and published by Prentice Hall in 2003. This book is considered as a complete reference for the Verilog HDL including [http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber20656&isYear2001 Verilog-2001] constructs). Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. The first edition of this book (ISBN 013-451675-3) was published by Prentice Hall in March, 1996. The book was soon embraced as a reference book for chip designers and as a textbook for digital design courses at universities.
Organization
This book is organized into three parts.
Part 1, Basic Verilog Topics, covers all information that a new user needs to build small Verilog models and run simulations. Part 1 contains nine chapters.
Part 2, Advanced Verilog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, user defined primitives, programming language interface, logic synthesis and advanced verification techniques are covered. Part 2 contains six chapters.
Part 3, Appendices, contains information useful as a reference. Useful information, such as strength-level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog examples is included. Part 3 contains six appendices.
Contents
This book progresses from the basic Verilog HDL concepts to the most advanced concepts in digital design. It covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. This book progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis. In the end, it devotes a chapter to advanced verification techniques such as formal verification, high level verification languages (HVLs), hardware acceleration and hardware emulation.
Chapters included in the book are as follows:
# Overview of Digital Design with Verilog HDL
# Hierarchical Modeling Concepts
# Basic Concepts
# Modules and Ports
# Gate-level Modeling
# Dataflow Modeling
# Behavioral Modeling
# Tasks and Functions
# Useful Modeling Techniques
# Timing and Delays
# Switch-level Modeling
# User-defined Primitives
# Programming Language Interface
# Logic Synthesis with Verilog HDL
# Advanced Verification Techniques
Appendices included in the book are as follows:
# Strength Modeling and Advanced Net Definitions
# List of PLI Routines
# List of Keywords, System Tasks and Compiler Directives
# Formal Syntax Definition
# Verilog Tidbits
# Verilog Examples
Target Audience
The book is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products.
About the Author
Samir Palnitkar has 18 years of industry experience and is a noted authority on digital chip design. He is currently the General Manager at AirTight Networks, Inc., a wireless security company. Samir Palnitkar is also the author of another digital chip design book titled “Design Verification with e” (ISBN 013-141309-0) published by Prentice Hall in October 2003.
Verilog References
E. Sternheim, Rajvir Singh, Rajeev Madhavan, Yatin Trivedi, Digital Design and
Synthesis with Verilog HDL, Automata Publishing Company, 1993. ISBN 0-9627488-2-X.
Donald Thomas, Phil Moorby, The Verilog Hardware Description Language , Fourth
Edition, Kluwer Academic Publishers, 1998. ISBN 0-7923-8166-1.
Stuart Sutherland, Verilog 2001 - A Guide to the New Features of the Verilog Hardware
Description Language, Kluwer Academic Publishers, 2002. ISBN 0-7923-7568-8.
Stuart Sutherland, The Verilog PLI Handbook: A User's Guide and Comprehensive
Reference on the Verilog Programming Language Interface, 2nd Edition, Kluwer
Academic Publishers, 2002. ISBN 0-7923-7658-7.
Douglas Smith, HDL Chip Design: A Practical guide for Designing, Synthesizing and
Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, TX, 1996,
ISBN 0-9651934-3-8.
Ben Cohen, Real Chip Design and Verification Using Verilog and VHDL, VhdlCohen
Publishing, 2001. ISBN 0-9705394-2-8.
J. Bhasker, Verilog HDL Synthesis: A Practical Primer, Star Galaxy Publishing, 1998.
ISBN 0-9650391-5-3.
J. Bhasker, A Verilog HDL Primer, Star Galaxy Publishing, 1999. ISBN 0-9650391-7-X.
James M. Lee, Verilog Quickstart, Kluwer Academic Publishers, 1997. ISBN 0-7923992-7-7.
Bob Zeidman, Verilog Designer's Library, Prentice Hall, 1999. ISBN 0-1308115-4-8.
Michael D. Ciletti, Modeling, Synthesis and Rapid Prototyping with the Verilog HDL,
Prentice Hall, 1999. ISBN 0-1397-7398-3.
Janick Bergeron, Writing testbenches: Functional Verification of HDL Models, Kluwer
Academic Publishers, 2000. ISBN 0-7923-7766-4.
Lionel Bening and Harry Foster, Principles of Verifiable RTL Design, 2nd Edition,
Kluwer Academic Publishers, 2001. ISBN 0-7923-7368-5.
Stuart Sutherland, Verilog HDL Quick Reference Guide, Sutherland Consulting, OR,
2001. ISBN 1-930368-03-8.
Rajeev Madhavan, Verilog HDL Reference Guide, Automata Publishing Company, CA,
1993. ISBN 0-9627488-4-6
Stuart Sutherland, Verilog PLI Quick Reference Guide, Sutherland Consulting, OR, 2001.
ISBN 1-930368-02-X.
Verilog Resources
* www.testbench.in - Verilog for Functional Verification - free online tutorial with many examples.
* verilog-ams - Accellera Verilog Analog Mixed-Signal Group website.
* Asic-World - Extensive free online tutorial with many examples.
* Verilog.net - Premiere List of Verilog Resources on the Internet.
* Digital Computer Courses ("Politehnica" University of Bucharest).
*
* A Verilog Designers Guide - Doulos. Good for beginners.
* Lots of Verilog Examples - asic.co.in.
* - Stuart Sutherland of Sutherland HDL, Inc.
* Perl CPAN module for parsing $readmem files
Verilog Standards Development
* [http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber20656&isYear2001 IEEE Std 1364-2001] - The official standard for Verilog 2001 (not free).
* - Working group for Verilog (inactive).
* - Working group for SystemVerilog (replaces above).
* Verilog syntax - A description of the syntax in Backus-Naur form. This predates the IEEE-1364 standard.
* Verilog-AMS - Accellera mixed signal extensions to Verilog
* - A heavily linked BNF syntax for Verilog 2001 (generated by EBNF tools).

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