Shakti Processor Project
The Indian Institute of Technology Madras is developing six RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the Internet of Things (IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies.
The SHAKTI processor project aims to build 6 variants of processors based on the RISC-V ISA from UC Berkeley (www.riscv.org). The project will develop a complete reference SoC for each family which will serve as an exemplar for that category of processor. While the cores and most of the SoC components (including bus and interconnect fabrics) will be in open source, some standard components like PCIe controller, DDR controller and PHY IP will be proprietary 3 part IP.
Processor Variants
C class microcontrollers
* 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
* Optional memory protection Very low power static design
* Fault Tolerant variants for ISO26262 applications
* IoT variants will have compressed/reduced ISA support
I class processors
* 64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications
* Devices aimed at networking applications will have dual-quad issue support
* Other features - shared L2 cache, AXI bus, threading support
M Class processors
* Enhanced variants of the I-class processors aimed at general purpose compute, low end server and mobile applications
* Enhancements over I class - large issue size, quad-threaded, up to 8 cores, freq up to 2.5 Ghz, optional NoC fabric
S class processors
* 64-bit superscalar, multi-threaded variant for desktop/server applications.
* 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
* RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
* Hybrid Memory Cube support
* 256/512 bit SIMD
* Specialized variants with FUs for database acceleration, security acceleration.
* Experimental variants will be used as test-bed for our Adaptive System Fabric project which aims to design a data-center architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques
H class processors
* 64-bit in-order, multi-threaded, HPC variant with 32-100 cores
* 512 bit SIMD
* Interconnect TBD
* Goal is 3-5 + Tflops (DP, sustained)
T class processors
Experimental security oriented 64-bit variants with tagged ISA, single address space support, decoupling of protection from memory management.
Processor Interconnect
We are also developing a processor to processor cache-coherent interconnect to allow building of multi-socket S class systems. The interconnect is based on the RapidIO interconnect. We are investigating a two tier scheme where a MOESI/MESIF style scheme is used for 2-8 socket systems anda directory based scheme for larger configurations (max 256 sockets)
Design Approach
The approach is to built optimal (high performance) building blocks that can be shared among the variants and then add variant specific blocks. The above variants are just canonical references and the Shakti family will see variants that will be hybrids.
When possible, we have also provided the Synopsys and Xilinx synthesis results for each module.
Final versions will contain the full BSV code, the generated Verilog code, testbenches, verification IP and FPGA support files.
Contributors
Project Co-ordinators
* Prof. V. Kamakoti
* G.S.Madhusudan
Research Scholars
* Neel Gala
* Bodduna Rahul
* Arjun Menon
Reference
Official Website: http://rise.cse.iitm.ac.in/shakti.html
Article on RapidIO: http://www.rapidio.org/2014/08/iit-madras-open-source-processor-project/
Conference Paper: https://www.researchgate.net/publication/301709828_SHAKTI_Processors_An_Open-Source_Hardware_Initiative
News Update: https://linuxgizmos.com/linux-boots-on-new-shakti-risc-v-chip/
The SHAKTI processor project aims to build 6 variants of processors based on the RISC-V ISA from UC Berkeley (www.riscv.org). The project will develop a complete reference SoC for each family which will serve as an exemplar for that category of processor. While the cores and most of the SoC components (including bus and interconnect fabrics) will be in open source, some standard components like PCIe controller, DDR controller and PHY IP will be proprietary 3 part IP.
Processor Variants
C class microcontrollers
* 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
* Optional memory protection Very low power static design
* Fault Tolerant variants for ISO26262 applications
* IoT variants will have compressed/reduced ISA support
I class processors
* 64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications
* Devices aimed at networking applications will have dual-quad issue support
* Other features - shared L2 cache, AXI bus, threading support
M Class processors
* Enhanced variants of the I-class processors aimed at general purpose compute, low end server and mobile applications
* Enhancements over I class - large issue size, quad-threaded, up to 8 cores, freq up to 2.5 Ghz, optional NoC fabric
S class processors
* 64-bit superscalar, multi-threaded variant for desktop/server applications.
* 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
* RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
* Hybrid Memory Cube support
* 256/512 bit SIMD
* Specialized variants with FUs for database acceleration, security acceleration.
* Experimental variants will be used as test-bed for our Adaptive System Fabric project which aims to design a data-center architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques
H class processors
* 64-bit in-order, multi-threaded, HPC variant with 32-100 cores
* 512 bit SIMD
* Interconnect TBD
* Goal is 3-5 + Tflops (DP, sustained)
T class processors
Experimental security oriented 64-bit variants with tagged ISA, single address space support, decoupling of protection from memory management.
Processor Interconnect
We are also developing a processor to processor cache-coherent interconnect to allow building of multi-socket S class systems. The interconnect is based on the RapidIO interconnect. We are investigating a two tier scheme where a MOESI/MESIF style scheme is used for 2-8 socket systems anda directory based scheme for larger configurations (max 256 sockets)
Design Approach
The approach is to built optimal (high performance) building blocks that can be shared among the variants and then add variant specific blocks. The above variants are just canonical references and the Shakti family will see variants that will be hybrids.
When possible, we have also provided the Synopsys and Xilinx synthesis results for each module.
Final versions will contain the full BSV code, the generated Verilog code, testbenches, verification IP and FPGA support files.
Contributors
Project Co-ordinators
* Prof. V. Kamakoti
* G.S.Madhusudan
Research Scholars
* Neel Gala
* Bodduna Rahul
* Arjun Menon
Reference
Official Website: http://rise.cse.iitm.ac.in/shakti.html
Article on RapidIO: http://www.rapidio.org/2014/08/iit-madras-open-source-processor-project/
Conference Paper: https://www.researchgate.net/publication/301709828_SHAKTI_Processors_An_Open-Source_Hardware_Initiative
News Update: https://linuxgizmos.com/linux-boots-on-new-shakti-risc-v-chip/
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