|
Sajib Kumar Mitra
|
|
S.K. Mitra is working as an Engineer at Bangladesh Bank, the central Bank of Bangladesh. At the same time he is also doing research in several areas of Computation such as Reversible Computing, Quantum Computing, etc. He has published several papers on Reversible Programmable Logic Arrays (RPLA), Cost Minimization of Reversible Full Adder, Reversible Barrel Shifter, etc. Currently he is working on generalization of equivalent optimized quantum realization of reversible circuits. History Sajib Kumar Mitra was born in Khepupara, a small town in Patuakhali, Bangladesh. He was the second among three sons of Joydeb Mitra and Jotshana Rani. He was the best friend of his elder brother and both were in about the same age (one year gap). His elder brother's name is Rajib Kumar Mitra and younger brother is Anike Chandra Mitra. Sajib has completed his S.S.C and H.S.C degree from Khepupara High School (2002) and Mozahar Uddin Biswas College (2004), respectively. Then he came to Dhaka from completing B.Sc degree from any reputed university. In 2005, he was qualified in an admission test exam at University of Dhaka and selected as a student of Computer Science and Engineering Department. So, in 2005 is the turning point of his life and he has concentrated on doing research in Reversible Computing under supervision of young Assist. Lecturer Ahsan Raja Chowdhury, Dept. of C.S.E, DU. Finally, he completed his undergraduate degree in 2010 with all first class and published his first paper in Reversible Computing in India VLSI Design Conference in 2012. He started his MS degree under supervision of renown professor, Sir Hafiz Md. Hasan Babu, Prof. and Ex-Chairman Dept. of Computer Science and Engineering, University of Dhaka. He has published an ACM conference paper based on his MS thesis in 2012 in GLS-VLSI 2012. At the same time he has worked multiple software company, including Samsung Bangladesh R&D Center, Gulshan-I from year 2010 to 2012. After working more than one year he left Samsung because of his research interest in work and it was happening so early rather expected. Then join Ahsanullah University of Science and Technology (AUST) as a part-time lecturer. In Sep, 2012 he joined with Daffodil International University (DIU) Bangladesh as a full-time lecturer and concentrated in research again. In 2014, he completed his MS degree after finishing lots of problematic situations. Finally, he again switched that job to Govt. Services as Engineer in Bangladesh bank. International Conference Papers # Reversible Programmable Logic Arrays (2016) # Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis (2014) # On the Analysis of Reversible Booth’s Multiplier (2014) # Minimum cost fault tolerant adder circuits in reversible logic synthesis (2012) # Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays (2011) # An efficient approach for designing and minimizing reversible programmable logic arrays (2012) # Efficient Design of Check Circuit to detect Multiple Cell Errors in Reversible Logic Synthesis (2011) # Efficient Approach to design Reversible Fault Tolerant Cyclic Redundancy Check Circuit (2011) # Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis (2011) Journal Paper # Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis (Extended Version) (2012). Ongoing Research # Reversible Decoder, Reversible Sub-tractor, Reversible Multiplexer. : 
|
| < Prev | Next > |
|---|
Main Menu
| Home |
| Articles |
| Search |
| Submit Article |
| Contact Us |
| Donate to Wikibin |
